The semiconductor industry continually strives to increase device performance by reducing the distance between individual devices, and by reducing the size of the devices themselves. Unfortunately, this continuing reduction in device dimensions has begun to adversely effect the performance and the reliability of integrated circuits.
Specifically, the reduction in transistor gate length has made it more difficult to control the drain saturation current of submicron transistors, especially submicron PMOS transistors. The source and drain regions of a transistor are fabricated using dopants that rapidly diffuse through silicon. Present integrated circuit fabrication processes, however, cannot uniformly and repeatedly control the lateral diffusion of these dopants. As a result, submicron transistors often have non-uniform drain saturation currents. This occurs because the overlap between the gate electrode and the source and drain regions cannot be repeatedly controlled, due to the uncontrolled lateral diffusion of the dopants which are used to form the source and drain regions.
Accordingly, a need exists for a method to form transistors in an integrated circuit which have improved drain saturation currents.